A conventional flat-cell or contactless Flash memory array employs bit lines and source lines that are diffused into a silicon substrate to reduce the overhead for drain and source contacts. FIGS. 1A and 1B show conventional contactless Flash memory array arrangements such as described in U.S. Pat. Nos. 5,717,636 and 5,526,307, which are hereby incorporated by reference in their entirety. These contactless memories have global metal bit lines 180 that connect to bank select devices 170 and 175 in a number of banks. FIG. 1A shows a single bank 100, and FIG. 1B shows two banks 100A and 100B. In these memories, each metal bit line 180 connects via a pair of bank select devices 170 and 175 to two independent diffused bit lines 110 and 115 that share a diffused source line 120.
FIG. 1C conceptually illustrates the layout of a bank 100 in a conventional contactless Flash memory. In bank 100, n+ diffusion into a silicon substrate forms diffused bit lines 110 and 115 and diffused source lines 120. Polysilicon floating gates 130 (poly 1) overlie channel regions, which are between diffused bit lines 110 and diffused source lines 120. Polysilicon word lines 140 (poly 2) cross over portions of diffused bit lines 110 and diffused source lines 120 that form the drains and sources of memory cells and also overlie associated floating gates 130.
FIG. 1D shows a cross section along a word line 140 in bank 100. As shown in FIG. 1D, channel regions 117 in the silicon substrate separate drain regions of diffused bit lines 110 and 115 from source regions of diffused source lines 120. Floating gates 130 overlie respective channel regions 117, with a gate insulator (e.g., gate oxide layer) between floating gates 130 and underlying channel regions 117. Word lines 140 overlie floating gates 130 with an insulating layer between each word line 140 and the underlying floating gates 130 that are in a row corresponding to the word line.
Returning to FIG. 1C, diffused source lines 120 extend to ground lines 125 or a virtual ground structure (not shown) at one end of bank 100. Diffused bit lines 110 and 115 extend to respective bank select devices 170 and 175 at an end of bank 100 opposite ground lines 125.
Bank select devices 170 and 175 include transistors between respective diffused bit lines 110 and 115 and contacts to respective metal bit lines 180 that are typically part of a first metal layer. Generally, each metal bit line 180 extends over a number of banks and is connected to corresponding bank select devices 170 and 175 in each of the banks. Bank select lines 160 and 165 respectively control bank select devices 170 and 175 in bank 100 to determine whether diffused bit lines 110 or 115 in bank 100 are connected to respective metal bit lines 180. The architecture of bank 100 provides only one metal bit line 180 for each pair of diffused bit lines 110 and 115, and bank select signals on bank select lines 160 and 165 control whether metal bit lines 180 are electrically connected to even-numbered diffused bit lines 110 or odd-numbered diffused bit lines 115.
Another conventional architecture for contactless Flash memories is illustrated in FIG. 1E and described in U.S. Pat. No. 5,691,938, which is hereby incorporated by reference in it entirety. The memory of FIG. 1E includes one metal bit line 180 for each diffused bit line 110 and only requires a single bank select line 170 per metal bit line 180 in each bank.
FIG. 1F is a circuit diagram representing two banks 100A and 100B having the same structure as bank 100 of FIGS. 1C and 1D. As shown, diffused bit lines 110 provide a resistance R between each pair of adjacent memory cells 150 along the bit line and a parasitic capacitance C per memory cell 150. Similarly, each source line 120 has resistance R and parasitic capacitance C associated with each section of the source line 120 between memory cells 150.
A programming operation for a selected memory cell in bank 100 uses channel hot electron injection to change the charge on the floating gate 130 in the selected memory cell. The programming operation generally applies a positive programming voltage Vw to a selected metal line 180 associated with the selected memory cell and grounds diffused source lines 120 via ground line 125 in the selected bank. Activation of the selection signal on the bank select line 160 or 165 in the bank containing the selected memory cell applies the programming voltage Vw from the selected metal bit line 180 to an end of a selected diffused bit line 110. An opposite end of the source line 120 for the selected memory cell is grounded.
The drain-to-source voltage resulting across the selected memory cell during programming depends the total impedance along of the diffused bit line 110 or 115 and source line 120 between the points at which voltage Vw and ground are applied to the diffused lines. Contactless Flash memory designs generally limit the lengths of diffused bit and source lines 110 and 120 to control the total impedance and voltage (or iR) drop during programming. Additionally, bank select devices 170 and 175 must have a size sufficient to provide the current required for rapid programming despite the impedance in the diffused bit and source lines 110 and 120. Current contactless memories typically have banks with 32 to 128 memory cells 150 per diffused bit line 110, and bank select devices can occupy a substantial percentage of the area of a bank.
A contactless Flash memory architecture that reduces voltage drop that the impedance causes in diffused lines 110 and 120 during programming could permit larger banks with a larger number of memory cells and reduce the size or amount of overhead circuitry associated with the bank select devices in the contactless Flash memory.
In accordance with an aspect of the invention, a contactless Flash memory architecture provides bank select devices at both ends of each diffused bit line. The bank select devices simultaneously share the current load required for programming and can thus be made smaller than bank select devices in memory architectures having bank select devices at only one end of each diffused bit line. In one embodiment, of the invention, the number of memory cells in per column in a bank can be doubled if the bank includes bank select devices on opposite ends of each diffused bit line. Each of these bank select devices can be smaller than a bank select device used in an architecture having bank select devices at only one end of a bank.
In different embodiments, source or virtual ground contacts for diffused source lines in a bank can be located in the center of a bank, at one end of a bank, or at both ends of the bank.
One specific embodiment of the invention has a bank of memory cells that includes: a diffused bit line that is continuous between a first end and a second end in a substrate; a diffused source line in the substrate; a column of memory cells such as Flash memory cells that are between the diffused bit and source lines; an overlying bit line associated with the diffused bit line; a first bank select device; and a second bank select device. The first bank select device is between the bit line and the diffused bit line, and when activated, the first bank select device conducts from the overlying bit line a current that enters the first end of the diffused bit line. Similarly, the second bank select device is between the bit line and the diffused bit line, and when activated, the second bank select device conducts from the bit line a current that enters the diffused bit line at the second end of the diffused bit line.
Generally, each of the first and second bank select devices has a size such that current that flows through the bank select device during programming is insufficient by itself to program the memory cell in a required programming time, but the combination of the currents flowing through the first and second bank select devices during programming is sufficient to program the memory cell in the required programming time.
The diffused source line can be connected to an overlying virtual ground line. In alternative embodiments, the diffused source line has two contacts, one contact at each end of the diffused source line, or a single contact in a central portion of the bank.
The contacts from overlying bit lines to the bank select devices can either be near source line contacts or staggered with a column of memory cells separating each contact to bank select devices and the nearest contact to a diffused source line. In one embodiment, the bank includes a second diffused bit line and a second column of memory cells formed in and on the substrate with portions of the second diffused bit line and the diffused source line forming drain/source regions of the memory cells in the second column. A third bank select device when activated conducts a current that enters the first end of the second diffused bit line, and a fourth bank select device when activated conducts a current that enters the second end of the second diffused bit line. One contact structure has a first contact connecting the bit line to the first and third bank select devices and a second contact connecting the bit line to the second and fourth bank select devices. In an alternative contact structure, the third bank select device is between a second bit line and the second diffused bit line and when activated conducts the current that enters the first end of the second diffused bit line, and the fourth bank select device is between the second bit line and the second diffused bit line and when activated conducts the current that enters the second end of the second diffused bit line.
Another embodiment of the invention is programming method for a memory cell in a contactless Flash memory. The method includes: activating a word line associated with the memory cell to enable a current flow through the memory cell from a diffused bit line to a diffused source line; and simultaneously generating a first programming current that flows in a first direction along the diffused bit line to the memory cell and a second programming current that flows in a second direction along the diffused bit line to the memory cell, the second direction being opposite the first direction. The first and second programming currents can be simultaneously generated by biasing an overlying bit line to a programming voltage and simultaneously activating a first bank select device that is between the overlying bit line and a first end of the diffused bit line and a second bank select device that is between the overlying bit line and a second end of the diffused bit line. Additionally, both ends of the diffused source line can be grounded so that current flows in the diffused source line in both directions away from the memory cell.
Another embodiment of the invention is a method for reading a memory cell in a contactless memory. The method includes: activating a word line associated with the memory cell to a level that enable a current flow through the memory cell from a diffused bit line to a diffused source line if the memory cell is in a first threshold voltage state but does not enable current flow if the memory cell is in a second threshold voltage state; connecting a metal bit line to a first end and a second end of the diffused bit line; grounding the diffused source line; and sensing whether a significant current flows through the metal bit line. Grounding the diffused source line can be via a contact in a central portion of a bank containing the memory cell. Alternatively, grounding the diffused source line includes connecting opposite ends of the diffused source line to ground.